I am the designer of this project, and would like to thank magicalhippo who originally posted here about my work, I appreciate that my work can reach more people in that hopefully some might enjoy seeing and possibly even building it.
This reply is for people here interested in the design, who feel a certain nostalgia because I noticed there were some questions which I feel I would like to comment on to make a few things more clear, for interested users here.
I started out doing Z80 stuff since the 90s, and did a Z80 PC mainboard. It got me interested in also designing an XT system to learn from this and possibly it could benefit a later revision Z80 system because that was my favorite CPU. I did that until I found that the XT design was sufficiently user friendly and complete. The original XT schematics were relatively complete in terms of the schematics. I have seen some bare PCBs of my design being sold of my XT on a Russian website, which I was happy to see because I hope that anyone enthousiastic, feeling nostalgic about the XT machine and able to do so could have the chance to also build one. Usually you get 5 pieces from for example JLCPCB so there will be some excess boards left over. All the mainboards are not easy and require some skill level and understanding in order to be able to debug any timing related issues. It could be interesting for students for a school project.
Next I decided to look at the AT which is a completely different machine, and yet shared many similarities. The big appeal of the AT to me was the fact that the IBM team involved had the great foresight to make the 16 bit AT completely hardware and software compatible to the 8 bit XT machine. When you study the complete design, you can find that this is not a trivial matter and goes deeply into the core of the technology in order to be able to really have true backward compatibility. In doing this, the PC/AT paved the way for the industry standard to successfully evolve from it. The 16 bit 286 is limited but it deserves respect and served its role in giving humanity the PC technology. The clone builders then took off with the standard which has in it's core kept the original 5170 functionality inside it. It's pretty amazing for this machine to have survive in so many iterations of PC technology! To me this is a level of legendary invention by IBM and particularly thanks to Don Estridge.
The 5170 is a severely limited machine because it consists of a lot of TTL circuits which are vulnerable to timing problems and difficult to scale up in that configuration. The 5170 and similar TTL chipset boards are vulnerable and error prone in my experience, I tested 4 of these old boards and they all had some issues. In order to get the functionality I needed, I had to say goodbye to the TTL graveyard approach and venture into programmable logic. Initially I didn't want to do this because it's not open, but when I recreated more circuits hidden in the PAL chip U87, the scale of the whole design started to grow beyond what I am comfortable with integrating into a single mainboard, and being able to include some useful integrated I/O. The design files are shared so technically it's also openly known technology just in a programmable form. The CPLD chips are a little large, however they have the advantage of through hole sockets being possible. This makes the design more accessible for people who don't like SMD. There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system so I took the chip off again. My design does support the 80287 math coprocessor, I have tested this. Please keep in mind, this was literally my first prototype PCB concept of an AT design, and took me more than a year to develop. Before my work, the AT design was only partially known openly to the world. You can see some MAME files and some previous failed attempts to reverse engineer the U87 PAL. A big and important part was hidden inside PAL chip U87, which is now openly known in a functional schematic finally. Without knowing the logic inside U87, there is no chance to fully know the system and how it works. After the 5170 it's mostly all chipset based AT PCs and these chipsets are not known.
After I had replicated a functional 5170, the next goal was clock speed above the original 8MHz. I progressed into 16MHz and then targeted to replace the 82284 and 82288 control chips inside the existing system controller CPLD. This required some level of rewiring finally to patch in an oscillator IC for the new clock signal. A lot of the development work I have done so far is the same as what chipset developers have done before. So I could learn and understand the issues they had faced before in order to get to higher clock speeds and reduce the design in size. Simply replicating the logic in a CPLD comes with a lot of timing related challenges and issues which I have had to overcome in my development.
Please note, the original 5170 used a S-BUS or system bus. Directly behind this bus on the mainboard is the M-BUS or memory bus. So in principle it's possible to move the M-BUS onto a card into the ISA slot which is what I have done. Also note, the ISA bus is simply a CPU/system bus and has no real clock operation. It's only limited looking at the system as a whole in terms of how fast the entire system is able to operate. And that limit is not 8MHz. It's much higher, at least 18 to 20MHz, depending on the configuration. My design was originally intended to be a recreation of the 5170, however it turned out to have much bigger potential far beyond that design thanks to the CPLD chips. My design is not DRAM based, it's SRAM based. So no CAS/RAS involved and no refresh. I removed all refresh functions which are not needed and to some extent free up the CPU for a few more useful cycles per second.
The next step I am working on now is a combined 286/486 system which can swap the CPU. The 486 function will be at some level in 32 bit so it is planned to support all the faster DX2 and DX4 CPUs which evolved. I will use BGA FPGA chips which have much higher integration capability and higher clock rating. This design is in the same spirit as the first revision prototype, to redo the development which was done in the 90s, however I am using more modern technology which was not available at the time. However it's about the technology at its core to be openly known and published finally, and not being lost in time because of original machines dying off. Doing this design can preserve the historic technology in a reproducable form, it's fun to me and also allows to explore the further limits and efficiency of these CPUs, hopefully the FPGAs used will be able to do this in previously unseen levels. I will be using some modern RAM like DDR or such and let the FPGA control it and interface to the legacy CPU. That's the idea. Imagine running a 486 with the full memory in the same speed as cache chips. I don't know if that's possible but I will attempt it. For more details, check out the VCF thread. The new 286/486 development follows in the same thread which started with my 286 PC/AT design. In GitHub there are separate projects published for each of my design iterations.
Thanks for the additional history and context, and nice work. Clearly a non-trivial undertaking.
I stumbled over it while searching for some details on the turbo button my 286 had for a subthread in this[1] story.
When the 286 finally died we upgraded to a 468, but it was one of those Cyrix clones that could be run on a 386 motherboard. It worked very well overall, except there was some features missing which caused issues with a couple of games as I recall. Will be interesting to see if you can get the 486 working on this board as well.
Thanks for pointing me to this interesting other thread as well. I replied to this just now offering my theoretical two cents to the conversation.
Regarding the 486 support in my next iteration, it will be a huge work to get this going. The 486 has no 82284 and 82288 type of equivalent IC to get the system going initially, so I will need to depend completely on reading the Intel timing diagrams in the datasheet/book and developing the logic to create my own CPU state machine and the system control mechanisms. With the 286 I did this same work in the end, however with the 486 I will need to develop this right at the beginning to even be able to execute code and have a functional system. I will probably modify an existing 486 mainboard in order to test out my own system control circuits on the CPU in order to replace the existing ones from the chipset one by one. I will create a method as I go along in the process. Basically it involves first creating a predictive CPU state machine model, verify this against the actual CPU in operation and comparing everything with the datasheet diagrams. In my VCF thread anyone can read how I am going about this project, and how I did it with the 286.
I am preparing the work leading up to integrating the 486 CPU into the system so I am not reading into this specific documentation yet. That will come when I have all the PCB designs ready and I have everything built up for testing because the preparation itself is already a lot of work. I have been warned that designing FPGA logic is even harder than using CPLDs for this type of "asynchronous" functions as in an PC/AT system which are easy to be skewed by seemingly insignificant circuit changes in any area inside the FPGA. The compiler may completely "overhaul" the programmed file for the FPGA at any time which may pose a new challenge every time to fix the problems, that can occur at any moment during the project. Anyway it was kind of newold86 at VCF to give me a heads up about this. So it will be the trick to find ways of changing the core AT design to become more "immune" to compiler changes.
Another challenge using different types of 486 will of course be the CPU voltage which is different between different types and brands of the 486 CPU. So I will need to design an interface between the FPGA and the CPU which has a variable logic voltage on the side of the level shifters connected to the CPU. Then we have the interface between the FPGA and the 5V ISA slots and cards, and with the 32 bit connection to a VGA adapter it may also pose other challenges, I am still doing the research and preparation of the various modules incrementally, so I will know more details about the actual complexity later. As far as the RAM is concerned I also will need to look at the voltages involved which type of RAM is most compatible with the FPGA of choice. A lot of work ahead.
I got some support from Luca (Retro*Tech) from Italy, who offered to help me and donated a ST 486DX4V100, which will be one test subject for the project.
I will start testing the system using a custom 286 module just to verify lots of things like the ISA slots, onboard I/O and memory interface. There will be the chance to speed-test the 286 to its limits. I talked with user sqpat who is also doing very cool work. He overclocked some 286 CPUs to above 30MHz using a TOPCAT chipset mainboard. Not only is he doing that, he created a custom cooling solution to keep the CPU from burning out, and he is developing his own port of DOOM for the 286 called RealDOOM, where he is using Real mode of the 286 because the TOPCAT chipset is able to generate a paging system within the 640KB base memory area. So he can keep software in the lowest section running while flipping the pages to load in DOOM game data. A unique and cool approach, and a kind of challenge to get this port fully optimized and I would imagine it involves a lot of code rewriting and completely new game loading configuration and mechanisms.
Anyway, thanks for the interest magicalhippo, it's much appreciated.
>There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system
- reset (and COM1_CS/RTC_DS) is routed horizontally across the board on inner layer cutting ground plane in half right under Realtek and both CPLDs :o. Weak stitching top layer islands using sparse tiny high impedance Vias is not a good way of joining isolated grounds.
- only one Realtek VDD pin 17 is connected to power plane with thick via, rest are using tiny signal vias.
- one tht 100nF capacitor might not be enough to decouple Realtek, usually on ISA cards there are pairs of caps for every one of RTL8019 six VDD inputs. Personally I think 12 caps is total overkill, but there is some middle ground in between.
- Realtek differential TX output is routed along whole ISA J7 slot between pins, seemingly not a problem except it also goes between crystal pins (with interrupted ground, big no no) and over SD8-15 with no ground plane under. Once again ground plane is disrupted by signals being routed in it. This might lead to for example 20 MHz clock being coupled to upper part of data bus.
- looks like 1.8432M for UART also goes across whole board with no ground plane in places.
>In GitHub there are separate projects published for each of my design iterations.
Would it be possible to upload whole kicad project (pcb, sch)? Much easier to browse than gerbers re-imported into pcbnew.
- Whats the deal with RTC_CS from POWER_GOOD? Why additional redundant hex inverter generator for 32KHz?
- Power and reset generation seems very elaborate, 6 chips doing the work of two 7404 inverters and few RC pairs.
Am I correct in assuming those are leftovers from experimentation? Btw calling VBAT "VDD" was a funny trap, took me a good second to realize what was going on :)
I started out doing Z80 stuff since the 90s, and did a Z80 PC mainboard. It got me interested in also designing an XT system to learn from this and possibly it could benefit a later revision Z80 system because that was my favorite CPU. I did that until I found that the XT design was sufficiently user friendly and complete. The original XT schematics were relatively complete in terms of the schematics. I have seen some bare PCBs of my design being sold of my XT on a Russian website, which I was happy to see because I hope that anyone enthousiastic, feeling nostalgic about the XT machine and able to do so could have the chance to also build one. Usually you get 5 pieces from for example JLCPCB so there will be some excess boards left over. All the mainboards are not easy and require some skill level and understanding in order to be able to debug any timing related issues. It could be interesting for students for a school project.
Next I decided to look at the AT which is a completely different machine, and yet shared many similarities. The big appeal of the AT to me was the fact that the IBM team involved had the great foresight to make the 16 bit AT completely hardware and software compatible to the 8 bit XT machine. When you study the complete design, you can find that this is not a trivial matter and goes deeply into the core of the technology in order to be able to really have true backward compatibility. In doing this, the PC/AT paved the way for the industry standard to successfully evolve from it. The 16 bit 286 is limited but it deserves respect and served its role in giving humanity the PC technology. The clone builders then took off with the standard which has in it's core kept the original 5170 functionality inside it. It's pretty amazing for this machine to have survive in so many iterations of PC technology! To me this is a level of legendary invention by IBM and particularly thanks to Don Estridge.
The 5170 is a severely limited machine because it consists of a lot of TTL circuits which are vulnerable to timing problems and difficult to scale up in that configuration. The 5170 and similar TTL chipset boards are vulnerable and error prone in my experience, I tested 4 of these old boards and they all had some issues. In order to get the functionality I needed, I had to say goodbye to the TTL graveyard approach and venture into programmable logic. Initially I didn't want to do this because it's not open, but when I recreated more circuits hidden in the PAL chip U87, the scale of the whole design started to grow beyond what I am comfortable with integrating into a single mainboard, and being able to include some useful integrated I/O. The design files are shared so technically it's also openly known technology just in a programmable form. The CPLD chips are a little large, however they have the advantage of through hole sockets being possible. This makes the design more accessible for people who don't like SMD. There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system so I took the chip off again. My design does support the 80287 math coprocessor, I have tested this. Please keep in mind, this was literally my first prototype PCB concept of an AT design, and took me more than a year to develop. Before my work, the AT design was only partially known openly to the world. You can see some MAME files and some previous failed attempts to reverse engineer the U87 PAL. A big and important part was hidden inside PAL chip U87, which is now openly known in a functional schematic finally. Without knowing the logic inside U87, there is no chance to fully know the system and how it works. After the 5170 it's mostly all chipset based AT PCs and these chipsets are not known.
After I had replicated a functional 5170, the next goal was clock speed above the original 8MHz. I progressed into 16MHz and then targeted to replace the 82284 and 82288 control chips inside the existing system controller CPLD. This required some level of rewiring finally to patch in an oscillator IC for the new clock signal. A lot of the development work I have done so far is the same as what chipset developers have done before. So I could learn and understand the issues they had faced before in order to get to higher clock speeds and reduce the design in size. Simply replicating the logic in a CPLD comes with a lot of timing related challenges and issues which I have had to overcome in my development.
Please note, the original 5170 used a S-BUS or system bus. Directly behind this bus on the mainboard is the M-BUS or memory bus. So in principle it's possible to move the M-BUS onto a card into the ISA slot which is what I have done. Also note, the ISA bus is simply a CPU/system bus and has no real clock operation. It's only limited looking at the system as a whole in terms of how fast the entire system is able to operate. And that limit is not 8MHz. It's much higher, at least 18 to 20MHz, depending on the configuration. My design was originally intended to be a recreation of the 5170, however it turned out to have much bigger potential far beyond that design thanks to the CPLD chips. My design is not DRAM based, it's SRAM based. So no CAS/RAS involved and no refresh. I removed all refresh functions which are not needed and to some extent free up the CPU for a few more useful cycles per second.
The next step I am working on now is a combined 286/486 system which can swap the CPU. The 486 function will be at some level in 32 bit so it is planned to support all the faster DX2 and DX4 CPUs which evolved. I will use BGA FPGA chips which have much higher integration capability and higher clock rating. This design is in the same spirit as the first revision prototype, to redo the development which was done in the 90s, however I am using more modern technology which was not available at the time. However it's about the technology at its core to be openly known and published finally, and not being lost in time because of original machines dying off. Doing this design can preserve the historic technology in a reproducable form, it's fun to me and also allows to explore the further limits and efficiency of these CPUs, hopefully the FPGAs used will be able to do this in previously unseen levels. I will be using some modern RAM like DDR or such and let the FPGA control it and interface to the legacy CPU. That's the idea. Imagine running a 486 with the full memory in the same speed as cache chips. I don't know if that's possible but I will attempt it. For more details, check out the VCF thread. The new 286/486 development follows in the same thread which started with my 286 PC/AT design. In GitHub there are separate projects published for each of my design iterations.