If an atom is .1 - .5nm. That means the transistor wires are about 2-10 atoms thick. About what Richard Feynman predicted in his "plenty of room at the bottom". This is Amazing.
Is it possible to have a cube of 1nm transistors. Like a 100 million ^ 3. The cube would have size of 10cm w.d.h.
> Is it possible to have a cube of 1nm transistors. Like a 100 million ^ 3. The cube would have size of 10cm w.d.h.
Probably, but I suspect operating it would cause it to melt or explode :-) We could probably manufacturer 3D chips today (or more 3D than they are today), but from what I understand cooling them starts to become a major issue. (Not involved in chip design or manufacturing)
A total newb/layman question incoming; what exactly is the process that generates heat in CPUs?
Are there any known/theoretical ways in which information be transmitted and processed at the atomic/subatomic/quantum level without generating any heat?
a) Resistance. Every switching action is effectively charging a small capacitor (the transistor gate) through a wire. The wire has nonzero resistance. It will also usually be travelling through the gate of one or more transistors, which have a nonzero resistance ('Rdson').
b) Theoretically, all computing that 'destroys' information (overwriting one register value with another) costs entropy, although we're nowhere near that level at the moment - orders of magnitude away.
'Reversible' computing would theoretically not incur that cost.
It's been a while since I studied or worked with these things, but I think your explanation is wrong. A transistor (BJT or FET, doesn't matter) dissipates very little in either cut-off region or saturation region (Rdson -- in FETs). It's in the active region that the transistor drops the most voltage across itself and has a fair amount of current flowing through it. I don't feel like doing the math right now, so I'll just cite something[1]. Anyway, when you're switching transistor from one state to the other, it invariably spends a little bit of time going through the active region. This is where it heats up the most. In the saturation stage, most of the voltage drop is across pull-up or pull-down resistors, so the V drop across the transistor is quite small. The higher the frequency, the more time the transistor spends in the active region, switching between states. This is why a given processor runs hotter a higher frequency.
But like I said, it's been a while since I worked in this field, so if someone knows better please correct me.
You're correct that there is more dissipation in the active region, but the Rdson is not negligable because the transistors are so small and the gate voltages so low (1.8V or less).
Switching does dissipate power based on switching speed. For "big" macroscopic FETs driving motors you have a separate gate driver amplifier to handle this. Within a chip, there's a tradeoff because driving a particular gate fast requires a bigger transistor to do the driving, which in turn requires a bigger transistor to drive it - so if you're not careful you spend a lot of area.
Transistor sizes are individually tuned during the design process (usually 99% algorithmically, 1% human intervention). There's a whole bunch of tunable design parameters.
(Basically, for big FETs we pretend that the resistance between gate and drain-source channel is infinite. For tiny ones it's surprisingly small and electrons can simply tunnel through your "insulator").
I think you underestimate the switching losses. The transistor gate is effectively a capacitor. To turn in on the voltage must be raised above some threshold, and it's this gate charge = CV with an energy of 0.5CV^2 that is important. Then when the switch is turned off, that gate charge is dumped to ground and the energy is lost. All of these losses are related in digital logic, as the gate charge comes from the conduction current through some other transistor. So you are correct, and the parent is also correct. Fin-FETs are interesting because they put gate material on 3 sides of the channel which allows them to switch on and off more completely, but that also increases the gate capacitance which means more current and power to switch it.
Well, you just further explained pjc50's first explanation. I don't see anyplace where you disagree.
Besides, CMOS ensures there is very little current going through the circuit when it isn't switching. What increases the differences between a fully cut or saturated transistor and a switching one.
The effort to explore reversible computation technology is driven by a desire to fully minimise the energy cost of computation regardless of architectural details. Substrate or ISA make no difference, reversible computation operates under different rules of physics from non reversible computation.
Quite a lot of quantum information theory stuff is involved so I'm going to stop elaborating since I'm merely a layman with more than average interest in the fascinating topic of reversible computation. Best anyone interested in learning further read more from experts who really know what they are saying.
b) how is that theorethical? To change the bit information the old state needs to be 'lost' or dissipated as heat into the surroundings. How is this connected to a level from which we are orders of magnitude away (in which direction?).
Superconductivity is the other facet of the picture - it makes resistance effectively zero. Superconductivity usually needs very low temperatures (usually below the temperature that nitrogen is liquid).
For a CPU, you still need to address the transistors somehow. Chips aren't pure transistors, there are wires coming down from above, and that takes up a lot of space. As a result, vertical density doesn't scale as you might hope.
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Is it possible to have a cube of 1nm transistors. Like a 100 million ^ 3. The cube would have size of 10cm w.d.h.